1. Field of the Invention
The present invention relates to MOSFET device fabrication and more particularly to an ultra-thin body SOI MOSFET transistor and a fabrication method which allows for extending silicide depth in a gate-last process.
2. Description of the Background Art
The continued drive toward increasing integrated circuit densities has required continued reductions in channel size. As channels narrow, the short-channel effects within MOSFET devices become increasingly pronounced. The semiconductor industry, therefore, has sought solutions to alleviate, or bypass, these short-channel effects. Ultra-thin body, fully-depleted (FD) SOI MOSFET transistors are a suitable candidate for large-scale integration, as physical gate lengths below thirty five nanometers ( less than 35 nm) may be supported while retaining excellent short-channel performance. Short-channel effects include such adverse effects as threshold voltage roll-off and drain-induced barrier lowering. Ultra-thin body FD MOSFET devices provide additional benefits by way of reduced subthreshold slope and the elimination of parasitic junction capacitance. The use of fully-depleted SOI devices, however, is complicated by process difficulties that arise in forming silicide on the very thin source-drain junctions within an SOI device. As a result of these difficulties, the use of elevated source and drain contact areas is highly desirable.
Furthermore, as critical dimensions of transistors continue shrinking, the thickness of gate oxide is reduced such that direct tunneling leakage current through the very thin gate oxide, of typically less than twenty five Angstroms ( less than 25 xc3x85), increases dramatically. To suppress the severe gate leakage currents, a material with a high dielectric constant (high-k) can be preferably utilized to replace the conventional thermal oxide of the gate dielectric. To provide a high-k dielectric gate insulator with substantially the same effective thickness as oxide, the required physical thickness of high-k material increases. It will be appreciated that the direct current density is exponentially proportional to the physical dielectric thickness. Therefore, direct tunneling current flow through the gate insulator is significantly reduced. This is a primary motivation for utilizing high-k material as a gate insulator for very small transistors. Typically, high-k material may be selected from a metal oxide such as TiO2, Ta2O5, and so forth. A drawback to the use of high-k material, however, is with thermal stability, as metal atoms diffuse from the high-k material into the silicon when exposed to high temperatures above approximately seven hundred degrees Celsius ( greater than 700xc2x0 C.). Metallic diffusion poses a challenge in the fabrication process because the CoSi2 anneal temperature is performed in the range of from approximately eight hundred degrees Celsius and eight hundred twenty five degrees Celsius (800xc2x0 C.-825xc2x0 C.).
Therefore, a need exists for an ultra-thin body SOI MOSFET transistor having an elevated source and drain which is fabricated without the necessity of exposing the metal gate regions to high temperatures. The present invention satisfies those needs, as well as others, and overcomes deficiencies in previously developed solutions.
The present invention describes an ultra-thin body SOI MOSFET transistor and a gate-last fabrication method which provides elevated source-drain structures that support a thick silicide layer. The gate-last process facilitates utilizing thin high-k dielectric layers without the attendant diffusion effects associated with exposing a gate insulated with high-k material to high temperatures. Within the gate-last process, the gate insulator is formed for the device after polishing, recrystallization, and silicide formation. The method is practiced by retaining an insulating segment as a dummy gate xe2x80x9cplace-holderxe2x80x9d for the gate during the high-temperature processing steps, concluding with silicide formation. The segment of insulation comprising the dummy gate is then replaced with a physical gate comprising the desired high-k dielectric material and a gate electrode.
Specifically, the gate-last process of the present invention may be performed by way of example in the following steps. Patterning of an SOI wafer with an insulation layer to form silicon-insulator stacks. An amorphous silicon (a-Si) material is deposited to cover the silicon-insulator stacks and this is planarized to expose the insulator segment, and recrystallized. The junction is created beneath the insulator segment by performing the desired implantations. Annealing of the wafer is performed to recrystallize the silicon and activate the source-drain junction. Silicide is then formed in the surface of the recrystallized silicon to the desired depth. The insulator segment is removed to form a cavity which is then filled with a high-k dielectric material within which a metallic gate electrode is formed. The remainder of the MOSFET transistor may be fabricated according to conventional fabrication practices. An object of the invention is to fabricate an ultra-thin body SOI MOSFET transistor utilizing high-k dielectric and source-drain regions which are capable of supporting thick silicide formation.
Another object of the invention is to fabricate the ultra-thin body MOSFET transistor utilizing a high-k dielectric within the gate, while not exposing the dielectric to high temperatures during fabrication.
Another object of the invention is to fabricate the ultra-thin body MOSFET transistor utilizing conventional semiconductor materials and processing equipment.
Further objects and advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.